Design and FPGA implementation of a highly resource-efficient AES-256 encryption and decryption engine
- Growing demand for security in a wide range of fields gives raise to research for more efficient and modern methods. Additionally, the increase of systems that are deployed on hardware requires security to be embedded in small area to protect intellectual property, hardware, and integrity and confidentially of sensible data. Therefore, in this work a design and FPGA implementation of a highly resource-efficient AES-256 encryption and decryption engine is presented, as well as its comparison with state-of-the-art designs. The design shows a reduction in the resources used due to its architecture to reuse hardware throughout all the processing. The design is implemented on a Xilinx Artix-7 FPGA.
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Statistik
| Dokumentart: | Masterarbeit |
|---|---|
| Verfasserangaben: | Saul García Rodríguez |
| Betreuer: | Michael Karagounis |
| Sprache: | Englisch |
| URN: | urn:nbn:de:hbz:dm13-37471 |
| DOI: | https://doi.org/10.26205/opus-3747 |
| Jahr der Fertigstellung: | 2023 |
| Veröffentlichende Institution: | Fachhochschule Dortmund |
| Verleihende Institution: | Fachhochschule Dortmund |
| Datum der Abschlussprüfung: | 30.10.2023 |
| Datum der Freischaltung: | 26.10.2023 |
| Freies Schlagwort / Tag: | AES; FPGA; decryption; encryption; security |
| Seitenzahl: | 263 |
| Fachbereiche und Institute: | Informatik |
| DDC-Sachgruppen: | 000 Allgemeines, Informatik, Informationswissenschaft / 000 Allgemeines, Wissenschaft / 004 Informatik |
| Abschlussarbeiten: | Masterarbeiten |
| Lizenz (Deutsch): |  Creative Commons - CC BY - Namensnennung 4.0 International |
